1. Field of the Invention
This invention relates in general to a methodology to improve thermal and mechanical issues created by increased interconnect density, increased power levels by electronic circuits and increased levels of integrated electronic packaging. The present invention addresses these issues by encapsulating the circuitry within a circuit board structure which improves thermal, mechanical and integrated circuit device management over existing technologies known in the art today.
2. Description of Related Art
As circuitry in electronics becomes more and more complex, packaging of the circuitry has become more difficult. The common method for packaging integrated circuits and other electronic components is to mount them on Printed Circuit Boards (PCBs).
Recently, the application of new organic laminates in the construction of Multi -Chip-Modules (MCMs) has brought about significant improvements in the packaging cost and density of electronic circuits. Throughout this patent reference will be made to PCBs which shall be meant to include technologies associated with MCMs as well.
Computer chip clocking speeds have also increased. This increase in speed has made it difficult to couple chips together in such a way that the chip speeds are completely useable. Further, heat generated by integrated circuits has increased because of the increased number of signals travelling through the integrated circuits. In addition, as die size increases interconnect delays on the die are beginning to limit the circuit speeds within the die. Typically, the limitations of a system are contributed to, in part, by the packaging of the system itself. These effects are forcing greater attention to methods of efficiently coupling high-speed circuits.
Packaging the integrated circuits onto PCBs has become increasingly more difficult because of the signal density within integrated circuits and the requirements of heat dissipation. Typical interconnections on a PCB are made using traces that are etched or pattern plated onto a layer of the PCB. To create shorter interconnections, Surface Mount Technology (SMT) chips, Very Large Scale Integration (VLSI) circuits, flip chip bonding, Application Specific Integrated Circuits (ASICs), Ball Grid Arrays (BGAs), and the like, have been used to shorten the transit time and interconnection lengths between chips on a PCB. However, this technology has also not completely overcome the needs for higher signal speeds both intra-PCB and inter-PCB, because of thermal considerations, EMI concerns, and other packaging problems.
In any given system, PCB area (also known as PCB "real estate") is at a premium. With smaller packaging envelopes becoming the norm in electronics, e.g., laptop computers, spacecraft, cellular telephones, etc., large PCBs are not available for use to mount SMT chips, BGAs, flip chips or other devices. Newer methods are emerging to decrease the size of PCBs such as Build-Up-Multilayer technology, improved organic laminate materials with reduced thicknesses and dielectric constants and laser beam photo imaging. These technologies produce greater pressure to maintain the functionality of the PCB assembly in thermal, EMI and power application to the semiconductor devices. It can be seen, then, that there is a need in the art for a method for decreasing the size of PCBs while maintaining the functionality of PCBs. Further, there is a need for reducing the size of PCBs while using present-day manufacturing techniques to maintain low cost packaging.